MIL-PRF-20M
APPENDIX A
A.4.2 Combined style submission. Combined style submission shall be restricted as shown in table A-I.
Qualification of ER styles with standoffs will be extended to similar ER and non-ER styles without standoffs as
follows:
Will extend qualification to
Qualification to
ER without
non-ER without
ER standoff
standoff
standoff
CCR05
CCR05
CC05
CCR06
CCR06
CC06
TABLE A-I. Combined style submission.
Qualification
Number of
Number of
ER PIN
Non-ER PIN
Will qualify 1/
group
samples
samples
CCR05, 06, 07, 08, 09,
CCR05CG331GM
25
CC05CG331GM
16
CC05, 06, 07, 08, 09 in
CCR05CG332GM
25
CC05CG332GM
16
CG and CH characteristics;
I
CCR08CG472GM
25
CC08CG472GM
19
B, C, D, F, G, J, K cap. tolerance;
CCR08CG683GM
25
CC08CG683GM
19
200, 100, and 50 volts; FRL M.
CCR75, 76, 77, 78, 79,
CCR75CG750GM
25
CC75CG750GM
16
CC75, 76, 77, 78, 79 in
CCR75CG681GM
25
CC75CG681GM
16
II
CG and CH characteristics;
CCR79CG103GM
25
CC79CG103GM
19
B, C, D, F, G, J, K cap. tolerance;
CCR79CG823GM
25
CC79CG823GM
19
200, 100, and 50 volts; FRL M.
1/ ER style qualification will qualify equivalent non-ER style. Non-ER style qualification will qualify non-ER
style only.
2/ For qualification of style CCR05 with standoffs, see A.4.2.
A.5. SOLDER DIP (RETINNING) LEADS
A.5.1 Solder dip (retinning). The manufacturer may solder dip/retin the leads of capacitors supplied to this
specification, provided the solder dip process (see A.5.2) or an equivalent process has been approved by the
qualifying activity.
A.5.2 Qualifying activity approval. Approval of the solder dip process will be based on one of the following options:
a. When the original lead finish qualified was hot solder dip lead finish 52 in accordance with MIL-STD-1276
(NOTE: The 200 microinch maximum thickness is not applicable), the manufacturer shall use the same solder
dip process for retinning as was used in the original manufacture of the capacitor.
b. When the lead originally qualified was not hot solder dip lead finish 52 of MIL-STD-1276 as prescribed in
A.5.2a, approval for the process to be used for solder dip shall be based on the following procedure:
(1) Thirty samples of any capacitance value for each style and lead finish shall be subjected to the
manufacturer's solder dip process. The capacitors shall then be subjected to all group A, subgroup 1
post-electrical tests, with no defects allowed.
(2) Ten of the thirty samples shall then be subjected to the solderability test, with no defects allowed.
(3) The remaining 20 samples shall be subjected to the resistance to soldering heat test, followed by the
moisture resistance test, with no defects allowed.
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